Forward error correction is quite commonplace in modern wireless communications. Decoders of channel codes, such as may be present in a modem or other hardware component, utilise parallel processing turbo decoders to decode turbo codes of high speed user data in order to achieve data rates exceeding 40 Mbps in the 3G WCDMA (wideband code division multiple access) standard which is sometimes referred to as HSDPA (high speed downlink packet access). Many other radio access technologies also require turbo coding of user data.
Such high user data rates in HSDPA and other technologies require that a turbo decoder process data in parallel, typically four or eight soft data bits at a time. In order to do so one has to solve parallel access contentions because a turbo decoder processes soft data bits in two different orders, an ascending order and an interleaved order. Butterfly networks are a well known technique for routing soft data bits between a decoder core and eight (or four) memories (memory spaces). One prior art reference by the inventor herein which details butterfly networks for turbo decoding purposes is U.S. Pat. No. 8,051,239 entitled Multiple Access for Parallel Turbo Decoder.
In very general terms, U.S. Pat. No. 8,051,239 discloses solution of a given multiple access function and the control bits which control the individual switches of the butterfly network can be resolved from that multiple access function. The original memory space addresses are used together with a desired parallel access scheme. Since conceiving the invention in U.S. Pat. No. 8,051,239 the inventor herein has determined that this technique can be improved as is detailed below.